Core Capability · Level 2.05

Embedded Cyber-Physical & Real-Time Systems

Microcontrollers, DSPs, FPGAs, real-time operating systems, deterministic networks, firmware, edge compute and hardware-in-the-loop control.

Revision 1.9.1 · Phase 2 content and navigation review

Public-safe engineering gateway: this page explains responsibilities, interfaces, work products and review evidence without publishing application-specific dimensions, algorithms, allowables or unreleased performance data.

Engineering Role

Why This Gateway Exists

This gateway places computation inside the physical control loop. It partitions deterministic control, communications, diagnostics and local intelligence across processors, firmware and real-time networks with bounded timing behavior.

Questions This Team Must Close

Which functions require deterministic execution and what are their timing budgets?
How should workloads be partitioned across MCU, DSP, FPGA, SoC or edge compute?
Which network and device interfaces preserve control integrity?
How will startup, update, fault recovery and diagnostic behavior be controlled?

Controlled Engineering Scope

Six Level-3 Topic Pages

Each daughter page defines a focused technical responsibility, the interfaces it must control and the evidence expected as the design matures.

Level 3.1 · MCU, DSP, FPGA and SoC architecturesPartitioning deterministic control, signal processing, safety and compute workloads across embedded processing devices.Level 3.2 · RTOS and deterministic schedulingReal-time task architecture, priorities, timing budgets, interrupt behavior and bounded execution under load.Level 3.3 · Firmware, device drivers and diagnosticsLayered embedded software, hardware abstraction, device control, boot behavior, logging and service diagnostics.Level 3.4 · EtherCAT, CANopen, PROFINET and ModbusDeterministic and industrial communications architecture, timing, topology, device profiles and fault containment.Level 3.5 · Edge computing and local intelligenceOn-machine processing for perception, optimization, anomaly detection and bounded autonomy near physical equipment.Level 3.6 · Hardware-in-the-loop and real-time testReal-time plant simulation and I/O stimulation used to verify controllers before or alongside physical integration.

Cross-System Integration

Interface Discipline

Embedded control sits at the boundary between sensors, power electronics, actuators, networks, safety functions and supervisory software; those interfaces must share controlled timing and state definitions.

Requirements and operating modes

Physical and energy interfaces

Signals, timing and data ownership

Safety, security and fault behavior

Configuration and lifecycle change

Verification and acceptance evidence