AURORA ENGINEERING SYSTEMSELECTRICAL ENGINEERING SYSTEMS
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Category 11 · Topic 02

Stackups & PCB Materials

Layer order, copper weights, dielectric selection, reference planes and fabrication-compatible stackup definition.

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Stackups & PCB Materials technical rendering
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Engineering overview

A PCB stackup is an electromagnetic, thermal and manufacturing structure. Layer order, dielectric thickness, copper weight, resin/glass construction and reference-plane assignment collectively determine impedance, return-path quality, manufacturability, stiffness and thermal spreading.

Stackup definition should be negotiated with the fabricator early. Treating it as a late documentation exercise can force impedance changes, via changes or layer-count changes after routing has already converged.

Core concepts

Reference planesHigh-speed traces need continuous nearby return structures; plane assignment is part of routing architecture.
Dielectric propertiesRelative permittivity and loss affect impedance and attenuation and vary with material system and frequency.
Copper geometryThickness, roughness and etch behavior influence resistance, impedance and fabrication tolerance.
Symmetry and buildBalanced constructions reduce warp/twist risk and simplify sequential lamination and fabrication control.

Engineering workflow

  1. Translate signal, power, thermal and density needs into a provisional layer count.
  2. Assign reference planes and power structures before choosing exact dielectric thicknesses.
  3. Select a material family with the fabricator based on electrical loss, thermal needs, environment, availability and cost.
  4. Model controlled-impedance structures using the fabricator’s actual construction data, not nominal textbook values.
  5. Freeze the stackup with fabrication notes and ensure layout rules match the released construction.

Tradeoffs & failure modes

  • Using generic dielectric constants instead of process-specific values.
  • Routing critical signals across plane voids or layer transitions without return continuity.
  • Ignoring copper roughness or dielectric loss in high-speed/RF applications.
  • Changing material or dielectric thickness without re-validating impedance and timing.
Planned page assets

Visual and technical content lane

  • Primary explanatory diagram or cutaway.
  • One comparison or design-trade graphic.
  • At least one real engineering example after source audit.
  • Applicable standards or manufacturer reference pointers.
  • Public-safe HTML derived from controlled documentation when useful.